Accelerated Multi-Phase Packet Classification Architecture Using Internal Buffer

Traditionally, Internet routers only perform best effort service by processing each incoming packet in the same manner. With the emergence of new applications, packet classification is essential for supporting advanced Internet applications, such as network security and QoS provisioning. As the packet classification on multiple-fields is a difficult and time consuming problem, Internet routers need to classify incoming packet quickly into flows. In this paper, we present multi-phase packet classification architecture using an internal buffer for fast packet processing. Using internal buffer between address pair searching phase and remained fields searching phases, we can hide latency cones from the characteristic that search times of source and destination header fields are different. The proposed architecture is easy to apply to different needs due to its simplicity and generality.